1. Field of the Invention
The present invention relates to light valves, and in particular, to pixel cell arrays for light valves which utilize sublithographic isolation based upon the formation of dielectric spacer structures.
2. Description of the Related Art
Liquid crystal displays (LCDs) are becoming increasingly prevalent in high-density projection display devices. These display devices typically include a light source which passes light through a light valve.
One of the methods for producing colors in a liquid crystal display is to sequentially project light having a wavelength corresponding to a primary color onto a single light valve. Color sequential light valves create a spectrum of color within the range of the human perception by switching between a set of discrete primary colors. Typically, red, green, and blue are the primary tri-stimulus colors used to create the remaining colors of the spectrum.
Specifically, during projection of each primary color, the light intensity is modulated such that combination of the intensities of the primary colors in sequence produces the desired color. The frequency of switching between the primary wavelengths by the light valve should be sufficiently rapid to render discrete primary states indistinguishable to the human eye.
Two factors dictate the minimum frequency necessary for switching. The first factor is the ability of the human eye to detect the discrete primary colors (e.g., red, green, blue). At slower than ideal switching speeds, the human eye will detect a flicker and the primaries may not blend.
The second factor determining the frequency of switching is the video refresh rate. During display of video images, the individual frames must be refreshed at frequencies undetectable to the human eye.
The net frequency of switching demanded by the combination of sequential color blending and video refreshing is beyond the capabilities of light valves that utilize thick ( greater than 1 xcexcm) liquid crystal (LC) transducers. However, thin ( less than 1 xcexcm) liquid crystal transducers have been successfully fabricated. These thin LC transducers demonstrate adequate color sequential blending at video refresh rates. One example of such a thin LC transducer pixel cell structure is disclosed in U.S. Pat. No. 5,706,067, to Colgan et al.
In general, the conventional thin LC transducer pixel cells possess enhanced responsiveness due to the decreased volume of liquid crystal material between the top and bottom plates. A smaller volume enables the liquid crystal to shift orientation more quickly and in response to a lower applied voltage.
FIG. 1 shows a cross-sectional view of adjacent thin LC transducer pixel cells in a conventional light valve. Light valve portion 100 comprises adjacent pixel cells 110a and 110b having liquid crystal (LC) material 111 sandwiched within gap 106 between a top plate and a bottom plate. Top plate 102 is composed of a translucent material, typically glass. The bottom plate is formed by the reflective metal pixel electrodes 112a and 112b of adjacent pixels 110a and 110b, respectively.
Pixel electrodes 112a and 112b are separated and electrically isolated by trench 118. Pixel electrodes 112a and 112b lie on top of an upper intermetal dielectric layer 128 that is one component of interconnect scheme 104. Interconnect 104 overlies capacitor structures 118a and 118b formed within underlying silicon substrate 105. Underlying capacitors 118a and 118b are in electrical communication with pixel electrodes 112a and 112b, respectively, through metal-filled vias 140 and middle interconnect metallization layer 124 and lower interconnect metallization layer 122.
FIGS. 2AA-2DB illustrate the steps of the conventional process for forming an array of pixel cells in a light valve. For purposes of convention, all FIGS. 2_A illustrate a top view of the pixel cell, all FIGS. 2_B illustrate a cross-sectional view of the pixel cell along line A-Axe2x80x2 of the FIG. 2_A.
FIGS. 2AA-2AB illustrate the starting point for the conventional process for fabricating a thin LC transducer pixel cell. Starting structure 200 is created by forming an upper intermetal dielectric layer 212 over a lower interconnect metallization layer 214. A central portion of upper intermetal dielectric layer 212 is then etched to form via 216. A liner (not shown) typically composed of a Ti/TiN layer combination, is then formed on the walls of via 216, and via 216 is filled with metal (typically CVD Tungsten). Excess metal is then removed from the surface of upper dielectric layer 212, typically by a combination of etching and chemical-mechanical polishing (CMP).
FIGS. 2BA-2BB illustrate formation of the metal pixel electrode in accordance with the conventional process. Metal pixel electrode layer 206 is formed over the entire surface of the pixel cell.
FIGS. 2CA-2CB illustrate patterning of a photoresist mask 207 over pixel electrode layer 206. FIGS. 2DA-2DB show the etching of regions of pixel electrode layer 206 unmasked by photoresist 207, to form a plurality of intersecting trenches 218, followed by stripping of photoresist mask 207. Intersecting trenches 218 in turn define a plurality of discrete pixel cell electrodes 230.
Fabrication of the thin LC transducer pixel cell is completed by forming an alignment surface (not shown) for the LC material positioned on top of the pixel electrode. Forming this alignment surface is a two step process. First, a dielectric film (typically polyimide) is deposited on top of the pixel electrode. Second, the dielectric film is scored by a rubbing wheel, which traverses the surface of the pixel cell and gouges the alignment surface in a uniform direction. Liquid crystal material is then placed within the cell, and a top glass plate is secured to the tops of the support pillars.
The conventional fabrication process described above in FIGS. 2AA-2DB is adequate to produce functional thin LC transducer pixel cells. However, the conventional process flow suffers from a number of disadvantages.
One problem is that the step of defining and etching the inter-pixel trenches requires an additional masking step. This masking step carries with it penalties in terms of additional defects and higher cost.
Another problem is that the minimum spacing between adjacent pixels is dictated by the limits of resolution of the photolithographic process employed. This limitation is manifested in the step of patterning the mask to form the trenches in the pixel electrode layer, as shown above in FIGS. 2CA-2CB. For example, in a 0.3 xcexcm linewidth photolithographic technology, the distance across trench 218 of FIGS. 2DA-DB could be no less than 0.3 xcexcm.
The closer together the pixels of the array, the better the array will perform. This is particularly true with respect to minimizing leakage of incident light between pixel electrodes through the interconnect and into the underlying substrate, as there is less inter-pixel spacing to allow the passage of incident light. Close proximity between pixels also reduces unwanted optical artifacts attributable to interruption in the continuous pixel array backplane by topography of inter-pixel isolation structures.
Therefore, there is a need in the art for a process of forming an array of pixel cells where inter-pixel spacing between pixels is not constrained by photolithographic parameters, thereby enabling formation of arrays having greater pixel cell densities and enhanced resolution and clarity.
The present invention provides a process flow for forming an array of pixel cells that does not rely upon photolithography to define inter-pixel isolation. Instead, adjacent pixels of the array are electrically insulated from one another by dielectric spacer structures formed by the deposition and etching of a dielectric layer conforming to raised features of a sacrificial layer. The thickness of the sidewall spacers is determined by the conditions under which the dielectric material forming the spacers is deposited. The deposition rate of dielectric material can be carefully controlled to produce spacers having a thickness of substantially less than the minimum line width of a given photolithography system. In this manner, inter-pixel isolation in accordance with the present invention can result in fabrication of pixel arrays having much greater cell densities than found in conventional arrays.
A process flow for forming a pixel cell array in accordance with one embodiment of the present invention comprises the steps of forming a sacrificial layer on top of an upper intermetal dielectric layer, forming a photoresist mask over the sacrificial layer in a checkerboard pattern which includes a plurality of masked squares but which excludes corners of the masked squares, and etching unmasked portions of the sacrificial layer to stop on the upper intermetal dielectric layer to leave a raised portion of the sacrificial layer having a top and sidewalls. The photoresist mask is removed, and a first dielectric layer is formed over the upper intermetal dielectric layer and the top of the sacrificial layer, the first dielectric layer conforming to the sidewalls. The first dielectric layer is then etched to remove the first dielectric layer over the upper intermetal dielectric layer while leaving vertical dielectric spacer structures along the sidewalls. The raised portions of the sacrificial layer are then removed to leave the dielectric spacer structures, and a metal layer is formed over the upper intermetal dielectric layer and the dielectric spacer structures. The metal layer is then subjected to chemical-mechanical polishing to form a substantially planar metal electrode surface including intervening dielectric structures.
An apparatus in accordance with one embodiment of the present invention comprises an array of pixel cells arranged in a checkerboard pattern having a first set of squares alternating with a second set of squares, the first set of squares and the second set of squares formed from a first metal layer and lacking corners, and further comprises dielectric spacer structures having a thickness intervening between the first set of squares and the second set of squares.
The features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings.